In conventional reproduced signal processors, in order to extract a clock synchronous with recorded data, an input reproduced signal is quantized by an A/D converter, a frequency error and a phase error are calculated by a digital circuit based on the quantized data, the digital correction amounts are converted into analog values by a D/A converter, and oscillation frequency control of a VCO (voltage controlled oscillator) is performed (see, for example, Patent Document 1). FIG. 20 shows a block configuration of a feedback timing extractor. By performing such feedback control, a clock for driving the A/D converter and the digital portion is synchronized with a reproduced signal. Regarding decoding of data, since the clock and the quantized data can be synchronized, a decoding process can be performed based on this data.
In contrast to this, a reproduced signal processor employing a feedforward control scheme using a frequency synthesizer which is operated at a fixed rate has also been discussed in, for example, Patent Document 2. FIG. 21 shows a block configuration of the feedforward scheme. In this scheme, an A/D converter which quantizes a reproduced signal with a clock having a constant cycle (fixed rate) is used, an edge position of a synchronous clock is estimated based on a quantized digital data sequence and the fixed-rate clock, and the quantized data is interpolated, and also, the fixed CLK is thinned to generate a pseudo-synchronous clock Data CLK which is pseudo-synchronous therewith, and a decoding process is performed using these pieces of data and the pseudo-synchronous clock.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-8315    Patent Document 2: Japanese Unexamined Patent Application Publication No. H08-161829